1. Field of the Invention
The present invention relates to a content addressable memory, and particularly to a content addressable memory having a redundant repair function of repairing a faulty memory cell row with a spare redundant memory cell row.
2. Description of the Background Art
As one of major applications of memory devices, there is a CAM (Content Addressable Memory), which receives an input data and compares it with storage data (retrieval data) forming retrieval information to determine matching or mismatching between them. This kind of CAM is used, e.g., in a data processing system for address comparison in an operation of determining cache hit/mishit, which is performed during cache access for determining whether required data is stored or not.
On the other hand, ordinary memory devices such as SRAMs (Static Random Access Memories) or DRAMs (Dynamic Random Access Memories) are provided with spare redundant memory cell rows as redundant circuits. When there is a faulty memory cell row, it is replaced with a spare redundant memory cell row to repair the faulty memory cell row. Thereby, manufacturing yield of memory devices can be improved, and such redundant circuit technology has been generally used.
However, the CAM has memory cell rows, which are significantly different in structure from those of the ordinary memory device. For repairing a memory cell row in the CAM, the repairing must be performed not only in address selection (decoding), which is executed when reading and writing data, but also in a function (encoding) of successively providing matched addresses in accordance with a priority after a data retrieving operation.
Due to the function and the circuit structure peculiar to the CAM, the faulty memory cell row cannot be repaired without difficulty.
However, Japanese Patent Laying-Open No. 2002-260389 has disclosed a structure, which mutually converts logical addresses (externally applied addresses) and physical addresses (addresses to be used actually and internally) for executing the redundant repair of the memory cell row. More specifically, a shift operation of shifting a memory cell row, which corresponds to an address higher (or lower) than a faulty memory cell row, is executed based on a faulty address of the faulty memory cell row and a logical address. Thereby, the redundant repair of the faulty memory cell row is executed with the redundant memory cell row according to the structure disclosed in the above publication.
In the above publication, however, the faulty address is once predecoded, and then the shift operation is executed based on a result of this predecoding and a result of decoding of input of the ordinary logical address. Therefore, it is necessary to arrange a decode circuit of a relatively large circuit scale.
Accordingly, it is necessary to ensure a sufficiently large layout area for the decode circuit, resulting in a problem that the memory device requires a large circuit area.
In the above publication, the result of predecoding of the faulty address by the predecode circuit is used for executing the shift operation. More specifically, for comparing this result of the predecoding with the result of decoding of the logical address, the result of the predecoding is transmitted for every memory cell row. This increases the number of signal lines transmitting the predecode signals from the predecode circuit to the respective memory cell rows. Due to the increase in number of the signal lines, therefore, it is necessary for circuit design to give sufficient consideration to restrictions on lines and interconnections. This results in a problem that the circuit design is complicated. In particular, the number of interconnections for the predecode signals further increase in accordance with the bit length of the address. Therefore, the above problem becomes particularly remarkable when an array of a large capacity is to be constructed.